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SDRAM Memory Upgrades

Synchronous dynamic random access memory (SDRAM) is dynamic random access memory (DRAM) that is synchronized with the system bus. Classic DRAM’s interface is asynchronous – it responds as quickly as possible to changes in control inputs while SDRAM’s interface is synchronous – because it is synchronized with the computer's system bus it waits for a clock signal before responding to control inputs. An internal finite state machine is driven by the clock that pipelines (the chip can accept a new command before completing processing the previous one) incoming commands, permitting the a more complex pattern of operation on the chip than an asynchronous DRAM and enables higher speeds. A pipelined write command can be immediately followed by another without pausing for the data to be written to the memory array. In a pipelined read, the requested data appears following a fixed number of clock pulses (latency) after the read instruction during which additional instructions can be sent. Latency is an important consideration when purchasing SDRAM. SDRAM is also available registered for systems such as servers and workstations that require more flexible scalability.

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History

The concept of synchronous DRAM has been known since at least the 1970s and saw use in early Intel processors. Yet it was decades later in 1993 when Samsung introduced its KM48SL2000 synchronous DRAM that SDRAM began to be universally accepted in the technology industry. Because of its greater performance, by 2000 SDRAM had replaced almost all other types of DRAM in modern computers.

Early SDRAM was slower than comparable burst EDO DRAM as a result of additional logic. SDRAM internal buffering’s ability to interleave operations to multiple banks of memory increases effective bandwidth.

In 1993 JEDEC formally adopted its first SDRAM standard and has since adopted those for DDR, DDR2 and DDR3 SDRAM. Today, in essence all SDRAM is manufactured in compliance with JEDEC standards.